In evaluating a design constructed with a given process technology, it is needed to be known gate delay for a particular circuit. A ring oscillator can be used to generate measurements of gate delays. In the ring oscillator, a series of gates are coupled front to back, and it is measured how many oscillations the ring has in a given time period, and then divides by the number of gates. This information is then fed into a software simulator/emulator.
In certain circuit simulation techniques used to calculate delays for static timing analysis, the time it takes for the crest of a first pulse to migrate its way through a gate is calculated. However, there is a problem with this approach. There can be a problem when transition times of a pulse after the first pulse are not captured, such as because clocking periods of insufficient duration are not noticed. This can lead to an inability of the conventional software technologies to detect some of the types of timing failures that can occur in certain types of circuit, particularly clock pulse forming circuits.
Therefore, there is a need for a way to measure propagation delay that addresses at least some of the problems associated with conventional measurements of propagation delay.